There is a trade-off between operating speed and power consumption in designing a CMOS image sensor (CIS). Accordingly, a current CMOS image sensor technology employs a column-parallel analog-to-digital converter (ADC) architecture to reduce the power consumption while improving the operating speed. A readout circuit with the column-parallel ADC architecture, however, should be highly integrated to match the small size of the photo sensing pixel, and this is why a single-slope ADC having a simple structure is mainly used.
In a CMOS image sensor having the column-parallel architecture, however, adjacent analog-digital-converters may not be separated far enough apart to prevent interference due to the small pixel size, and thus coupling noise may occur between adjacent analog-to-digital converters.
Furthermore, interferences between adjacent analog-digital-converters may also cause banding noise. When a plurality of column-parallel analog-to-digital converters convert analog pixel signals into digital signals, the completion timings of the analog-to-digital conversion may vary depending on the amplitude of the analog pixel signal. As a result, analog-to-digital converters performing the analog-to-digital conversion are affected by adjacent analog-to-digital converters through a current/voltage bias line connected to the column-parallel analog-to-digital converters in common, resulting in unwanted variation in analog-to-digital conversion values.
Since such banding noise occurs for various reasons in an image extraction process and degrades image quality, various tuning points are considered in circuit design in order to minimize the banding noise.
However, it is difficult to minimize the banding noise by simply adjusting the size of a transistor or the amount of a current because a variation in an operation speed or power can cause the performance degradation of an entire system.